Asic Design Verification Engineering Technical Leader

Cisco UK

Base: $183,800 - $263,600 (up to $303,100 in nyc);...
10+ years asic design verification experience
Systemverilog and uvm methodology expertise
Block to top-level dv environment leadership
The role involves leading the architecture and development of verification environments for Cisco's core Switching, Routing, and Wireless products

Job Summary

  • The role involves leading the architecture and development of verification environments for Cisco's core Switching, Routing, and Wireless products.
  • Candidates will collaborate with designers and software teams to debug issues during post-silicon bring-up and contribute to chip architecture definition.
  • The position offers a competitive salary range up to $303,100 in NYC Metro areas along with comprehensive benefits including equity and flexible vacation time.

Matching Summary

The role involves leading the architecture and development of verification environments for Cisco's core Switching, Routing, and Wireless products.

Salary

Base: $183,800 - $263,600 (up to $303,100 in NYC); Bonus/Equity: Eligible for annual bonuses and restricted stock units; Benefits: Medical, dental, vision, 401(k) match, paid parental leave, and flexible vacation.

Skills & Requirements

Must-have

  • 10+ years ASIC Design Verification experience
  • SystemVerilog and UVM methodology expertise
  • Block to top-level DV environment leadership

Nice-to-have

  • Prior people management experience
  • Post-silicon lab bring-up experience
  • Networking domain knowledge

Key Requirements

  • Bachelor's degree + 10 years or Master's + 8 years experience
  • Experience leading UVM verification methodology at cluster or full chip level
  • Proficiency in debugging, simulation models, and test plan development

Work Rights

Not specified

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