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Inteelabs is seeking a Senior Pre-silicon Verification Engineer specializing in clock generator IP verification to ensure the functional correctness of PLL/FLL designs. The position requires expertise in mixed-signal validation, collaboration across teams, and comprehensive verification methodologies.
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Job Summary
We are seeking a Senior Mixed Signal Verification Engineer specializing in clock generator IP verification to ensure functional correctness of PLL/FLL designs.
This role combines digital verification expertise with mixed-signal validation capabilities, requiring collaboration across architecture, RTL development, and analog design teams to deliver high-quality clock generation solutions.
We offer a total compensation package that ranks among the best in the industry, consisting of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
Matching Summary
Match Score: 75
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Inteelabs is seeking a Senior Pre-silicon Verification Engineer specializing in clock generator IP verification to ensure the functional correctness of PLL/FLL designs. The position requires expertise in mixed-signal validation, collaboration across teams, and comprehensive verification methodologies.
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