Sr Principal Design Verification Engineer - Soc Verification

NXP Semiconductors

Noida, India
System verilog, uvm methodology
Ahb, axi, chi, ace, apb protocols
Processor architecture, debug architecture
The performance verification team is responsible to qualify that the design architecture and implementation meets these goals with detailed metrics analysis and cross correlation across model, RTL, emulation, silicon

Job Summary

  • The performance verification team is responsible to qualify that the design architecture and implementation meets these goals with detailed metrics analysis and cross correlation across model, RTL, emulation, silicon.
  • The candidate is expected to develop in depth understanding of chip architecture and define/ develop performance verification scenarios to test design/ architecture and report bottlenecks/ optimization opportunities.
  • Working with cross domains - IP owners, Systems and Core design teams to achieve performance verification objectives.

Matching Summary

The performance verification team is responsible to qualify that the design architecture and implementation meets these goals with detailed metrics analysis and cross correlation across model, RTL, emulation, silicon.

Skills & Requirements

Must-have

  • System Verilog, UVM methodology
  • AHB, AXI, CHI, ACE, APB protocols
  • Processor architecture, debug architecture
  • Memory subsystems, caches, DDR controllers
  • C/C++/Python programming skills
  • Performance verification scenarios

Nice-to-have

  • Emulation platform execution and debug
  • Graphics/Multimedia/Networking IPs
  • Cross-domain collaboration

Key Requirements

  • Experience with HDL/HVL
  • Strong understanding Bus Protocols
  • Understanding of processor architecture
  • Understanding of memory subsystems
  • Programming skills in C/C++/Python
  • Domain knowledge in specific IPs

Work Rights

Not specified

Tailored Resume

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