Asic Design Verification Engineer | Uvm | Exp- 8+ Years
Cisco UK
7+ years asic design verification experience
Proficient in uvm and system verilog
Experience building test benches from scratch
The role involves architecting block, cluster, and top-level DV environment infrastructure while developing test plans using constraint random and advised stimulus
Job Summary
The role involves architecting block, cluster, and top-level DV environment infrastructure while developing test plans using constraint random and advised stimulus.
Candidates will ensure complete verification coverage through code implementation and review, including qualifying the design with Gate Level Simulations on netlist.
The position offers exposure to Cisco's Silicon One architecture and collaboration with designers and software teams during post-silicon bring-up.
Matching Summary
The role involves architecting block, cluster, and top-level DV environment infrastructure while developing test plans using constraint random and advised stimulus.
Skills & Requirements
Must-have
7+ years ASIC design verification experience
Proficient in UVM and System Verilog
Experience building test benches from scratch
Scripting with Perl or Python
Gate Level Simulation and RTL quality
Nice-to-have
Experience with Forwarding logic P4 parsers
Knowledge of emulation platforms Veloce Palladium
Formal verification skills iev vc formal
Protocol expertise PCIe Ethernet RDMA TCP
Collaboration with multi-functional teams
Key Requirements
Bachelor's or Master's degree in EE CE or related field
Minimum 7 years of related ASIC design verification experience
Hands-on experience with System Verilog constraints structures and classes