Senior Power Integrity Engineer - Lpu Packaging

NVIDIA

Base: 196,000 usd - 310,500 usd (level 5); 232,000...
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Power delivery design and optimization
Pdn targets (impedance, droop, noise)
Package-level pdn architecture
** NVIDIA is seeking a Senior Power Integrity Engineer for their LPU Packaging team, focusing on defining and optimizing power delivery systems for advanced GPU and chip-package-board designs. The ideal candidate will have extensive experience in power integrity within high-current, low-voltage applications, particularly in large GPUs or ASICs. **

Job Summary

  • Define best-in-class power delivery design and optimization practices from die/package through board, tray, and rack levels for the full product development cycle.
  • Architect package-level PDNs by collaborating with design teams on bump/ball maps, via structures, and decoupling strategies for FCBGA and 25D/3D integrations.
  • With highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology industry's most desirable employers.

Matching Summary

Match Score: 75

** NVIDIA is seeking a Senior Power Integrity Engineer for their LPU Packaging team, focusing on defining and optimizing power delivery systems for advanced GPU and chip-package-board designs. The ideal candidate will have extensive experience in power integrity within high-current, low-voltage applications, particularly in large GPUs or ASICs. **

Salary

Base: 196,000 USD - 310,500 USD (Level 5); 232,000 USD - 368,000 USD (Level 6); Equity and benefits eligible

Skills & Requirements

Must-have

  • Power delivery design and optimization
  • PDN targets (impedance, droop, noise)
  • Package-level PDN architecture
  • System-level PI design
  • Frequency-domain PDN impedance analysis
  • Time-domain transient/droop simulation

Nice-to-have

  • Leadership of end-to-end PI
  • Data center or cloud hardware experience
  • Co-design of SI and PI
  • Strong communication skills

Key Requirements

  • MS or PhD in Electrical Engineering or related field
  • 12+ years of relevant work experience in Power Integrity
  • Proven ownership of chip-package-board PDN design and sign-off
  • Hands-on experience with FCBGA, 25D/3D integration, HBM
  • Proficiency with simulation tools (PowerSI, RedHawk, etc.)
  • Experience executing lab measurements (VNAs, oscilloscopes)

Work Rights

Not specified

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