Cpu Pre-silicon Verification Engineer

Intel

Guadalajara, Mexico
Uvm-based verification environments
Systemverilog
Constrained-random verification
Ensure the functional correctness and robustness of CPU logic designs through state-of-the-art pre-silicon verification methodologies

Job Summary

  • Ensure the functional correctness and robustness of CPU logic designs through state-of-the-art pre-silicon verification methodologies.
  • Architect, build, and enhance scalable UVM-based (or similar) constrained-random verification environments.
  • Debug complex RTL and testbench failures, performing thorough root-cause analysis using simulation tools, waveforms, and formal methods.

Matching Summary

Ensure the functional correctness and robustness of CPU logic designs through state-of-the-art pre-silicon verification methodologies.

Skills & Requirements

Must-have

  • UVM-based verification environments
  • SystemVerilog
  • constrained-random verification
  • coverage-driven closure
  • RTL and testbench debugging

Nice-to-have

  • collaboration with architects and designers
  • mentoring junior engineers
  • enhancing verification infrastructure

Key Requirements

  • Bachelor's degree or higher
  • 5+ years experience or Master's degree with 3+ years
  • Digital logic design experience
  • Scripting language, C++, SystemVerilog
  • Unrestricted permanent right to work in Mexico

Work Rights

Unrestricted permanent right to work in Mexico

Tailored Resume

Cover Letter