Base: $151,000 to $251,800; bonus/equity: mbo bonu...
Onsite
Soc memory architecture design
Memory hierarchy and interface knowledge
Cache subsystem optimization
This role involves defining and driving the development of innovative SoC memory and cache subsystems for premium chipsets
Job Summary
This role involves defining and driving the development of innovative SoC memory and cache subsystems for premium chipsets.
Candidates will analyze PPA trade-offs to optimize memory subsystem performance, power consumption, and area utilization.
The position offers access to comprehensive benefits including medical, dental, vision, 401(k), and potential long-term incentive plans.
Matching Summary
This role involves defining and driving the development of innovative SoC memory and cache subsystems for premium chipsets.
Salary
Base: $151,000 to $251,800; Bonus/Equity: MBO bonus compensation and long term incentive plan eligible; Benefits: Medical, dental, vision, life insurance, 401(k), free onsite lunch, tuition assistance, paid time off, student loan program, wellness incentives
Skills & Requirements
Must-have
SoC memory architecture design
Memory hierarchy and interface knowledge
Cache subsystem optimization
PPA trade-off analysis
DDR LPDDR HBM standards
Nice-to-have
Cache coherence protocol experience
Android ecosystem familiarity
Arm architecture knowledge
System modeling expertise
Emerging memory technology trends
Key Requirements
6+ years experience with Bachelor's degree
4+ years experience with Master's degree
2+ years experience with PhD
Strong understanding of JEDEC memory standards
Ability to access export-controlled information
Work Rights
Must have ability to access export-controlled information or be eligible for government authorization