Not specified; not specified; competitive compensa...
Expert-level systemverilog and uvm knowledge
Deep understanding of mixed-signal design principles
Advanced debugging across rtl and gate-level simulations
This senior position involves significant influence on verification methodology adoption and technical decisions that impact crucial organizational objectives
Job Summary
This senior position involves significant influence on verification methodology adoption and technical decisions that impact crucial organizational objectives.
You will architect sophisticated verification environments and mentor junior engineers while collaborating across organizational boundaries to ensure product quality.
The role requires leading complex debugging efforts and driving functional and code coverage closure using advanced verification methodologies.
Matching Summary
This senior position involves significant influence on verification methodology adoption and technical decisions that impact crucial organizational objectives.
Salary
Not specified; Not specified; Competitive compensation and benefits
Skills & Requirements
Must-have
Expert-level SystemVerilog and UVM knowledge
Deep understanding of mixed-signal design principles
Advanced debugging across RTL and gate-level simulations
Extensive experience with Cadence or Synopsys EDA tools
Advanced proficiency in Python, Perl, TCL, or Shell scripting
Nice-to-have
Mentoring junior engineers and modeling professional behaviors
Leading post-silicon validation activities
Representing ADI as principal customer contact
Influencing verification methodology adoption across teams
Key Requirements
MS/PhD in Electrical Engineering or related field
7-10+ years of relevant digital design verification experience
US Citizenship, US Permanent Resident, or protected individual status required for export control compliance
Work Rights
Must be US Citizen, US Permanent Resident, or protected individual