The role is responsible for the physical design of advanced process digital ASIC, AI, and CPU chips alongside layout design for analog and digital components
Job Summary
The role is responsible for the physical design of advanced process digital ASIC, AI, and CPU chips alongside layout design for analog and digital components.
Candidates will handle multiple tasks including back-end physical implementation from gate-level netlist to GDSII with a focus on PPAC optimization.
The position requires a strong theoretical foundation in digital circuits and practical skills within the IC development process.
Matching Summary
The role is responsible for the physical design of advanced process digital ASIC, AI, and CPU chips alongside layout design for analog and digital components.
Skills & Requirements
Must-have
Advanced process digital ASIC design
Gate-level netlist to GDSII implementation
PPAC optimization under advanced processes
PR PV IR signoff experience
STA Spice signoff knowledge
Nice-to-have
Strong curiosity in new technologies
Knowledge transfer capability
Innovation ability in IC development
Exploration of advanced packaging
Key Requirements
Bachelor's degree or higher in relevant engineering fields