You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design-for-Test
Job Summary
You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design-for-Test.
Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
Matching Summary
You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design-for-Test.
Salary
Base: $210,600.00 - $350,800.00; Bonus/Equity: Not specified; Benefits: Medical, dental, vision, 401(k) with match, paid parental leave, disability, life insurance, flexible vacation
Skills & Requirements
Must-have
DFT implementation
ATE, in-system test, debug and diagnostics
Scan and BIST architectures
ATPG and EDA tools
System Verilog Logic Equivalency checking
Nice-to-have
Verilog design experience
DFT CAD development
Test Static Timing Analysis
Post silicon validation
Key Requirements
Bachelor's or Master's Degree in Electrical or Computer Engineering
10 years of experience
Jtag protocols, Scan and BIST architectures
ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime