Sr Engineer Design Engineering - Sram Bit Cell Enablement
GlobalFoundries
Sram bit cell enablement
Cadence virtuoso layout
Drc and lvs verification
Support technology teams across 22 nm fully depleted SOI and 12 nm finfet technologies, spanning bit cell kit layout, PDK enablement, and test structure verification
Job Summary
Support technology teams across 22 nm fully depleted SOI and 12 nm finfet technologies, spanning bit cell kit layout, PDK enablement, and test structure verification.
Analyze incoming designs for bit cell content and contribute to the maintenance and improvement of layout infrastructure for memory bit cells.
This role requires close cooperation with global internal teams and may involve some interaction with customers and IP providers.
Matching Summary
Support technology teams across 22 nm fully depleted SOI and 12 nm finfet technologies, spanning bit cell kit layout, PDK enablement, and test structure verification.
Skills & Requirements
Must-have
SRAM bit cell enablement
Cadence Virtuoso layout
DRC and LVS verification
SPICE simulation experience
semiconductor process flow knowledge
Nice-to-have
customer interaction
IP provider interaction
multicultural workplace
Key Requirements
Master’s degree in microelectronics, electrical engineering, physics, or related fields
Experience with scripting languages like Pearl, shell script, Python
Good understanding of semiconductor device physics
Good understanding and experience with SRAM bit cell functionality