A Senior/Staff VLSI Verification Engineer with 11-15 years of experience drives complex SoC/ASIC verification, focusing on UVM/System Verilog testbench architecture, Mix signal IP verification strategy, and post-silicon debug
Job Summary
A Senior/Staff VLSI Verification Engineer with 11-15 years of experience drives complex SoC/ASIC verification, focusing on UVM/System Verilog testbench architecture, Mix signal IP verification strategy, and post-silicon debug.
Key responsibilities include defining verification plans, guiding junior engineers, improving verification methodologies, ensuring coverage closure, and collaborating with architects for top-level verification.
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies).
Matching Summary
A Senior/Staff VLSI Verification Engineer with 11-15 years of experience drives complex SoC/ASIC verification, focusing on UVM/System Verilog testbench architecture, Mix signal IP verification strategy, and post-silicon debug.
Skills & Requirements
Must-have
System Verilog UVM testbench architecture
Mix signal IP verification strategy
post-silicon debug
System Verilog and UVM
RTL debug gate-level simulations
Python Perl Tcl scripting
Nice-to-have
guidance for junior engineers
collaboration with architects
customer-driven end-to-end solutions
Key Requirements
11-15 years of ASIC/SoC verification experience
Expert-level System Verilog, UVM, Verilog
Proficiency in JTAG/IJTAG/CRI/APB protocols
Experience with Synopsys VCS, Cadence Xcelium/JasperGold, Mentor Questa
B.E/B.Tech or M.E/M.Tech/MS in Electronics/VLSI Engineering