Functional Verification Engineer - Applied Ml

Cadence

**
Formal verification experience
Systemverilog uvm expertise
Jasper xcelium eda tools
** Cadence is seeking a Functional Verification Engineer specializing in applied machine learning to enhance pre-silicon verification processes. The ideal candidate will possess a strong background in ASIC verification methodologies, programming skills, and a collaborative spirit to innovate within a cutting-edge technology environment. **

Job Summary

  • This role involves developing agentic AI solutions using LLMs to accelerate pre-silicon design verification processes.
  • Candidates will collaborate with machine learning engineers to validate the output correctness and efficiency of AI-enhanced EDA tools.
  • The position offers the opportunity to work on the world's first agentic AI platform designed to autonomously verify chips with significant productivity gains.

Matching Summary

Match Score: 75

** Cadence is seeking a Functional Verification Engineer specializing in applied machine learning to enhance pre-silicon verification processes. The ideal candidate will possess a strong background in ASIC verification methodologies, programming skills, and a collaborative spirit to innovate within a cutting-edge technology environment. **

Skills & Requirements

Must-have

  • Formal verification experience
  • SystemVerilog UVM expertise
  • Jasper Xcelium EDA tools
  • Python programming skills
  • Verilog debugging capabilities

Nice-to-have

  • LLM and RAG framework knowledge
  • Agentic AI platform experience
  • Customer requirement engagement
  • Continuous learning mindset
  • Team collaboration skills

Key Requirements

  • BS degree with 4+ years experience OR MS with 2+ years
  • 3+ years in formal, SV/UVM, or OVM methodologies
  • PhD graduate eligible for new roles

Work Rights

Not specified

Tailored Resume

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