Senior/lead Dft Engineer

NXP Semiconductors

Noida, India
Soc dft implementation and verification
Scan architectures, jtag, boundary scan
Memory bist, atpg and lbist
Senior DFT engineer preferably with 10+ yrs experience in SoC DFT implementation and verification of scan architectures, JTAG, boundary scan, memory BIST, ATPG and LBIST

Job Summary

  • Senior DFT engineer preferably with 10+ yrs experience in SoC DFT implementation and verification of scan architectures, JTAG, boundary scan, memory BIST, ATPG and LBIST.
  • The engineer should be well versed in Verilog/VHDL RTL coding, automation, experienced in using Mentor DFT tool sets and reasonable acquaintance with Synopsys’s scan insertion and timing analysis tools along with standard linting tools.
  • The engineer needs to have hands-on experience in scan insertion, JTAG, LBIST, ATPG DRC and coverage analysis, Simulation debug with timing/SDF and post silicon debug.

Matching Summary

Senior DFT engineer preferably with 10+ yrs experience in SoC DFT implementation and verification of scan architectures, JTAG, boundary scan, memory BIST, ATPG and LBIST.

Skills & Requirements

Must-have

  • SoC DFT implementation and verification
  • scan architectures, JTAG, boundary scan
  • memory BIST, ATPG and LBIST
  • Verilog/VHDL RTL coding, automation
  • Mentor DFT tool sets
  • Synopsys scan insertion and timing analysis tools
  • scan insertion, JTAG, LBIST, ATPG DRC
  • Simulation debug with timing/SDF
  • post silicon debug

Nice-to-have

  • engaged curiosity
  • eagerness to constantly learn
  • independent judgment
  • strong interpersonal skills
  • flexibility

Key Requirements

  • 10+ yrs experience
  • BE/ME/B.Tech/M.Tech from reputed institutes
  • relevant industry experience
  • worked on more than one SoC, from start to end

Work Rights

Not specified

Tailored Resume

Cover Letter