Senior Hardware Verification Engineer

NXP

Hyderabad, India
Uvm-based testbench architecture
Systemverilog verification environments
Functional coverage closure process
The Senior ASIC Hardware Verification Engineer is responsible for ensuring the design meets all architectural specifications before tape-out through comprehensive verification planning and execution

Job Summary

  • The Senior ASIC Hardware Verification Engineer is responsible for ensuring the design meets all architectural specifications before tape-out through comprehensive verification planning and execution.
  • The role involves developing scalable, reusable verification environments and driving coverage closure to 100% using advanced stimulus and debugging techniques.
  • The engineer will provide technical leadership to junior engineers and integrate mixed verification methods including formal verification and hardware emulation.

Matching Summary

The Senior ASIC Hardware Verification Engineer is responsible for ensuring the design meets all architectural specifications before tape-out through comprehensive verification planning and execution.

Skills & Requirements

Must-have

  • UVM-based testbench architecture
  • SystemVerilog verification environments
  • Functional coverage closure process
  • Constrained-random stimulus development
  • Hardware failure debugging using waveforms
  • Formal Verification integration
  • Hardware Emulation for system tests

Nice-to-have

  • Technical leadership and mentorship
  • Power-aware verification features
  • Code review for testbench components

Key Requirements

  • Experience with UVM and SystemVerilog
  • Expertise in functional verification of ASICs
  • Proficiency in debugging hardware failures
  • Knowledge of formal verification tools
  • Experience with hardware emulation platforms

Work Rights

Not specified

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