Sr. Ip Logic Design Engineer

Intel Jobs

Santa Clara, California, US
$190,610.00-269,100.00 usd; not specified; competi...
Hybrid
Memory coherency protocols
Interconnect topologies
Rtl code in verilog/systemverilog
Intel is seeking a Senior IP Logic Design Engineer to architect and implement memory coherency protocols and interconnect topologies for data centers and AI SoCs. The ideal candidate will have a strong background in SoC design and memory systems, with expertise in RTL coding and collaboration with cross-functional teams

Job Summary

  • Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs.
  • Design and implement critical components of the memory fabric microarchitecture, including coherency controllers and interconnect blocks.
  • We offer a total compensation package that ranks among the best in the industry, including competitive pay, stock bonuses, and comprehensive benefit programs.

Matching Summary

Match Score: 85

Intel is seeking a Senior IP Logic Design Engineer to architect and implement memory coherency protocols and interconnect topologies for data centers and AI SoCs. The ideal candidate will have a strong background in SoC design and memory systems, with expertise in RTL coding and collaboration with cross-functional teams.

Salary

$190,610.00-269,100.00 USD; Not specified; Competitive pay, stock bonuses, and benefit programs

Skills & Requirements

Must-have

  • memory coherency protocols
  • interconnect topologies
  • RTL code in Verilog/SystemVerilog
  • performance modeling and analysis
  • cross-functional collaboration

Nice-to-have

  • AI/ML accelerator design
  • software-hardware co-design
  • workflow automation scripting

Key Requirements

  • MS/PhD in Electrical Engineering or related field
  • 10+ years SoC design experience
  • Expertise in memory coherency protocols
  • Strong knowledge of interconnect technologies
  • Proven RTL coding experience

Work Rights

Not specified

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