Join the core Cisco Silicon One Front-End Design team to develop the industry's largest-scale and most advanced devices
Job Summary
Join the core Cisco Silicon One Front-End Design team to develop the industry's largest-scale and most advanced devices.
Engineers are responsible for the full spectrum of chip design including definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
The role involves collaborating with verification and physical design teams to resolve bugs, close timing, and perform post-silicon validation.
Matching Summary
Join the core Cisco Silicon One Front-End Design team to develop the industry's largest-scale and most advanced devices.
Skills & Requirements
Must-have
RTL design experience with Verilog/SystemVerilog
3+ years of relevant engineering experience
B.Sc./M.Sc. in Electrical Engineering
Nice-to-have
MATLAB simulations and bit-exact modeling
Mixed-signal systems familiarity
Clock Domain Crossing (CDC) expertise
Key Requirements
B.Sc./M.Sc. in Electrical Engineering from a top university