#21940-physical Design Engineer

Qualitest Group

Bangalore, India
On-site
Physical layout of complex asics
Rtl to gdsii implementation
Floorplanning, power planning, placement, cts, routing
You will be responsible for implementing and optimizing the physical layout of complex ASICs from RTL to GDSII

Job Summary

  • You will be responsible for implementing and optimizing the physical layout of complex ASICs from RTL to GDSII.
  • You’ll collaborate closely with RTL design, verification, and DFT teams to ensure successful tape-out of high-performance, low-power silicon designs.
  • Contribute to flow development and automation to improve quality and efficiency.

Matching Summary

You will be responsible for implementing and optimizing the physical layout of complex ASICs from RTL to GDSII.

Skills & Requirements

Must-have

  • physical layout of complex ASICs
  • RTL to GDSII implementation
  • floorplanning, power planning, placement, CTS, routing
  • timing closure using STA tools
  • IR drop and EM analysis
  • physical verification (LVS/DRC)

Nice-to-have

  • hierarchical design methodologies
  • low-power design techniques (UPF)
  • advanced nodes (5nm or below)

Key Requirements

  • 5+ years of experience in ASIC physical design
  • B.E in Electronics/M.Tech in VLSI Engineering
  • proven tape-out record
  • hands-on experience with industry-standard tools
  • Good scripting skills (TCL, Python, or Perl)

Work Rights

Not specified

Tailored Resume

Cover Letter