Senior Design Verification Engineer Category Location Toronto, Ontario

Talentlab Inc

Toronto, Ontario, CA
On-site
Systemverilog and uvm
Constrained-random verification
Serdes phys, dsps, and mixed-signal analog designs
Our client is a key player in advancing digital technology by accelerating high-performance data communication

Job Summary

  • Our client is a key player in advancing digital technology by accelerating high-performance data communication.
  • The Digital Design Verification team fosters a collaborative, growth-oriented culture where engineers are encouraged to take on new challenges, learn continuously, and contribute to impactful projects.
  • Work closely with cross-functional teams—including Design, Systems, Analog, Firmware, and PD—to ensure final verification closure.

Matching Summary

Our client is a key player in advancing digital technology by accelerating high-performance data communication.

Skills & Requirements

Must-have

  • SystemVerilog and UVM
  • constrained-random verification
  • SerDes PHYs, DSPs, and mixed-signal analog designs
  • Python, Perl, C/C++, and GNU Make

Nice-to-have

  • leading and coordinating verification tasks
  • behavioral models of analog circuits
  • support bit-matching between RTL and MATLAB
  • integrate third-party VIPs
  • post-silicon validation and bring-up
  • cross-functional team collaboration

Key Requirements

  • 3 to 8 years of relevant experience
  • Knowledge of Ethernet and PCIe protocols
  • Familiarity with formal verification
  • Familiarity with power-aware UPF verification

Work Rights

Not specified

Tailored Resume

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