Principal Design Engineer – Ai Soc / Subsystem Lead

Intel

Folsom, California, United States
Base: $220,920.00-311,890.00 usd; bonus/equity: st...
Hybrid
10+ years electrical engineering experience
7+ years rtl design implementation
Asic/soc development background
Intel is seeking a Principal Design Engineer for their AI SoC organization, responsible for designing and validating complex SoC IP blocks for AI applications. The ideal candidate will have extensive experience in RTL design and implementation, as well as a strong background in architecture and verification collaboration

Job Summary

  • This role involves defining, implementing, and validating complex SoC IP blocks to meet stringent power, performance, and security requirements.
  • The successful candidate will collaborate across architecture, verification, and physical design teams to deliver high-quality silicon for next-generation AI solutions.
  • Intel offers a competitive total compensation package including stock bonuses, health benefits, retirement plans, and vacation time.

Matching Summary

Match Score: 85

Intel is seeking a Principal Design Engineer for their AI SoC organization, responsible for designing and validating complex SoC IP blocks for AI applications. The ideal candidate will have extensive experience in RTL design and implementation, as well as a strong background in architecture and verification collaboration.

Salary

Base: $220,920.00-311,890.00 USD; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, and vacation programs

Skills & Requirements

Must-have

  • 10+ years electrical engineering experience
  • 7+ years RTL design implementation
  • ASIC/SoC development background
  • Verilog/SystemVerilog proficiency
  • Microarchitecture definition skills

Nice-to-have

  • Mentorship of junior engineers
  • Cross-functional collaboration mindset
  • Python/TCL scripting automation
  • Secure development practices knowledge
  • Strong communication abilities

Key Requirements

  • Bachelor's or Master's degree in EE, CE, or CS
  • Minimum 10 years of professional experience
  • Minimum 7 years in RTL design for ASIC/SoC
  • Position of Trust background investigation required

Work Rights

Not specified

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