Ip Verification Engineer

Altera Corporation

Bengaluru, Karnataka, India
Systemverilog and uvm verification environments
5+ years asic or fpga design verification experience
Constrained-random test case development
The role involves designing and validating software abstractions for FPGA acceleration to support embedded and data center clients

Job Summary

  • The role involves designing and validating software abstractions for FPGA acceleration to support embedded and data center clients.
  • Candidates must develop robust verification environments using SystemVerilog and UVM while creating directed and random test sequences.
  • The position requires defining functional coverage metrics and utilizing automation scripts in Python or Perl to improve verification efficiency.

Matching Summary

The role involves designing and validating software abstractions for FPGA acceleration to support embedded and data center clients.

Skills & Requirements

Must-have

  • SystemVerilog and UVM verification environments
  • 5+ years ASIC or FPGA design verification experience
  • Constrained-random test case development
  • Coverage-driven verification methodologies
  • Python or Perl scripting for automation

Nice-to-have

  • Familiarity with AMBA protocols like AXI and PCIe
  • Experience with formal verification methods
  • Strong analytical and problem-solving skills
  • Collaborative cross-functional team environment

Key Requirements

  • Bachelor's or Master's degree in Electrical or Computer Engineering
  • 5+ years of experience in ASIC or FPGA design verification
  • Proficiency in Verilog, VHDL, and SystemVerilog
  • Hands-on experience with simulation tools like Synopsys VCS or Cadence Xcelium

Work Rights

Not specified

Tailored Resume

Cover Letter