Asic Design Verification Engineer Ii (co-op) - United States

Cisco UK

Maynard, United States
Base: $44,000.00 - $185,000.00; bonus/equity: not ...
Systemverilog /uvm
Systemc
Object-oriented verification methodologies
The ASIC Design Verification Co-Op Engineer will be a member of a team working on next generation 100G-1T coherent optical communications products

Job Summary

  • The ASIC Design Verification Co-Op Engineer will be a member of a team working on next generation 100G-1T coherent optical communications products.
  • This role is focused on verifying highly-complex ASICs that are used in these next-generation telecom systems.
  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.

Matching Summary

The ASIC Design Verification Co-Op Engineer will be a member of a team working on next generation 100G-1T coherent optical communications products.

Salary

Base: $44,000.00 - $185,000.00; Bonus/Equity: Not specified; Benefits: Medical, dental, vision insurance, 401(k) plan with Cisco matching contribution, paid parental leave, short and long-term disability coverage, basic life insurance, restricted stock units, paid time away

Skills & Requirements

Must-have

  • SystemVerilog /UVM
  • SystemC
  • object-oriented verification methodologies
  • ASIC verification techniques
  • develop detailed test plans
  • develop verification test benches

Nice-to-have

  • fast-learning, self-motivated
  • collaborative and passionate
  • process improvements
  • FPGA emulation efforts
  • DSP algorithms
  • modulation techniques

Key Requirements

  • Currently enrolled in a full-time graduate program
  • Knowledge of SystemVerilog /UVM
  • Knowledge of SystemC
  • Knowledge of C and/or C++

Work Rights

Not specified

Tailored Resume

Cover Letter