Not specified; not specified; competitive compensa...
Cadence virtuoso layout design
High-speed serdes architecture experience
Finfet technology node expertise
This role involves architecting and implementing high-speed analog and mixed-signal circuits for next-generation 50G/100G optical link solutions using advanced silicon photonics
Job Summary
This role involves architecting and implementing high-speed analog and mixed-signal circuits for next-generation 50G/100G optical link solutions using advanced silicon photonics.
Candidates will own the floor planning, transistor-level layout, and full custom mask design of analog and digital blocks while collaborating with global teams across Canada, the U.S., and India.
The position offers a collaborative environment focused on purposeful innovation with competitive compensation and benefits designed to support professional growth.
Matching Summary
This role involves architecting and implementing high-speed analog and mixed-signal circuits for next-generation 50G/100G optical link solutions using advanced silicon photonics.
Salary
Not specified; Not specified; Competitive compensation and great benefits
Skills & Requirements
Must-have
Cadence Virtuoso layout design
High-speed SERDES architecture experience
FinFET technology node expertise
DRC LVS EMIR verification flows
Analog mixed-signal circuit layout
Nice-to-have
Python or Skill scripting automation
Global team collaboration skills
First-pass silicon success focus
Low-power high-performance optimization
Key Requirements
BE/B.Tech or MS/M.Tech in Electrical Engineering
4+ years of AMS Layout Design experience
Hands-on experience with FinFET nodes 5nm and below
Eligibility for U.S. export control access
Work Rights
Must be eligible to access export-controlled information under U.S. law