Responsible for implementing Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs
Job Summary
Responsible for implementing Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
Matching Summary
Responsible for implementing Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
Skills & Requirements
Must-have
Design-for-Test (DFT) features
ATE, in-system test, debug
Jtag protocols, Scan and BIST
ATPG and EDA tools
Gate level simulation, debugging
Post-silicon validation and debug
Tcl, Python/Perl scripting
Nice-to-have
Innovative DFT IP development
Physical design signoff activities
Collaborating with multi-functional teams
Thrive in a multifaceted environment
Key Requirements
Bachelor's or Master’s Degree in Electrical or Computer Engineering
At least 10 years of experience
Knowledge of latest trends in DFT, test, silicon engineering