Asic Design Engineer, Sta

Cisco UK

Base: $152,500.00 to $219,200.00; bonus/equity: el...
Onsite
Asic design experience
Verilog/systemverilog programming
Static timing analysis (sta)
Join the Cisco Silicon One team to develop a unified silicon architecture for web scale networks

Job Summary

  • Join the Cisco Silicon One team to develop a unified silicon architecture for web scale networks.
  • The role involves closing timing at block, sub-chip, and full-chip levels while performing quality checks such as setup, hold, transition, and noise.
  • Employees are eligible for benefits including medical, dental, vision insurance, a 401(k) plan with matching contributions, and paid parental leave.

Matching Summary

Join the Cisco Silicon One team to develop a unified silicon architecture for web scale networks.

Salary

Base: $152,500.00 to $219,200.00; Bonus/Equity: Eligible for annual bonuses and restricted stock units; Benefits: Medical, dental, vision, 401(k), paid time off

Skills & Requirements

Must-have

  • ASIC Design experience
  • Verilog/SystemVerilog programming
  • Static timing analysis (STA)
  • Timing closure at block and chip levels
  • ECO task handling

Nice-to-have

  • Prior STA experience
  • Strong written communication skills
  • Strong verbal communication skills
  • PNR and Spice correlation experience

Key Requirements

  • Bachelor's degree in Electrical or Computer engineering with 5+ years experience
  • Master's degree in Electrical or Computer Engineering with 3+ years experience
  • PhD with 0 years of experience

Work Rights

Not specified

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