Digital Ic Design (senior To Staff Engineer)

Marvell

Competitive salary; 13th-month salary + performanc...
Rtl design with verilog or systemverilog
On-chip bus protocols axi ahb apb
Timing closure and coverage closure analysis
This role involves designing the latest high-performance AI silicon and critical high-speed interface IP for Marvell's core products

Job Summary

  • This role involves designing the latest high-performance AI silicon and critical high-speed interface IP for Marvell's core products.
  • The team consists of about eight problem solvers working on ultra-dense performance AI ASICs that serve major chip and tech companies.
  • Employees receive competitive salary, a 13th-month salary, performance-based bonuses, RSUs, and generous paid leave policies including recharge periods.

Matching Summary

This role involves designing the latest high-performance AI silicon and critical high-speed interface IP for Marvell's core products.

Salary

Competitive salary; 13th-month salary and performance-based bonus; RSUs included

Skills & Requirements

Must-have

  • RTL design with Verilog or SystemVerilog
  • On-chip bus protocols AXI AHB APB
  • Timing closure and coverage closure analysis
  • Lint and CDC check execution
  • UVM based test bench understanding

Nice-to-have

  • Knowledge in PCIe NVMe CXL implementations
  • Scripting skills in PERL Python TCL
  • C/C++ programming background
  • Firmware development support experience

Key Requirements

  • Minimum BSEE degree required
  • 1 to 3 years of digital design experience
  • Eligibility for US export control access

Work Rights

Must be eligible to access export-controlled information under US law

Tailored Resume

Cover Letter