Job Summary

• Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
• Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).
• Define and track functional and code coverage metrics to ensure verification completeness and drive coverage closure.

Matching Summary

Skills & Requirements

Key Requirements

• 5+ years of experience
• Bachelor's or Master's degree
• ASIC or FPGA design verification
• SystemVerilog
• UVM-based testbenches

Work Rights