Asic Dft Engineer

Broadcom

Fort Collins, Colorado, United States
Base: $108,000 - $172,800; bonus/equity: discretio...
Asic dft specification and implementation
Scan insertion and compression
Atpg vector generation and debugging
The successful candidate will lead DFT programs from chip level specification through implementation, verification, and production release, working on various SoC DFT activities including architecture, test insertion, pattern generation, coverage improvement, and yield enhancement

Job Summary

  • The successful candidate will lead DFT programs from chip level specification through implementation, verification, and production release, working on various SoC DFT activities including architecture, test insertion, pattern generation, coverage improvement, and yield enhancement.
  • Broadcom offers a competitive and comprehensive benefits package including medical, dental, vision, 401(K) with company matching, Employee Stock Purchase Program, paid holidays, sick leave, and vacation time.
  • Broadcom is an equal opportunity employer and considers qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, or other protected characteristics.

Matching Summary

The successful candidate will lead DFT programs from chip level specification through implementation, verification, and production release, working on various SoC DFT activities including architecture, test insertion, pattern generation, coverage improvement, and yield enhancement.

Salary

Base: $108,000 - $172,800; Bonus/Equity: Discretionary annual bonus and equity awards; Benefits: Medical, dental, vision, 401(K) matching, ESPP, paid leave

Skills & Requirements

Must-have

  • ASIC DFT specification and implementation
  • Scan insertion and compression
  • ATPG vector generation and debugging
  • Memory BIST insertion and verification
  • Test vector generation and silicon debug
  • DFT coding using TCL, PERL, PYTHON, C++
  • Collaboration with physical design and test teams

Nice-to-have

  • Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST
  • Experience with Tessent SSN
  • Project management capabilities
  • Strong problem solving and root cause analysis
  • Statistical process control and data analysis
  • Customer and cross-functional team interaction
  • Innovating DFT solutions for advanced nodes

Key Requirements

  • Bachelor's degree in Electrical/Electronic/Computer Engineering with 8+ years experience or Master's degree with 6+ years experience
  • Strong background in IO and Analog DFT, ATPG, Scan, BIST
  • Experience with DFT tools such as DFT Compiler, Mentor TestKompress, TetraMax, Fastscan
  • Knowledge of IEEE1149.1, IEEE1149.6, IEE1687, IJTAG, ICL, PDL standards
  • Experience working with ATE and silicon bring-up
  • Ability to work in multi-disciplined, cross-department environment

Work Rights

Not specified

Tailored Resume

Cover Letter