Asic Sta Engineer

Cisco UK

New York City Metro Area, US
Base: $135,800.00 - $252,000.00; bonus/equity: not...
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Static timing analysis (sta)
Verilog/systemverilog programming
Asic design experience
** Cisco is seeking an ASIC Design Engineer for its Acacia team, focusing on high-speed optical interconnect products. The role involves developing extraction and static timing analysis methodologies while collaborating with the Physical Design team. **

Job Summary

  • As an ASIC Design Engineer on the STA team, you will play a pivotal role in extraction and static timing analysis (STA) flow development, convergence strategies, and correlation between PNR, Spice, and STA, while working alongside the Physical Design team.
  • Develop methodologies, guidelines, and checklists to streamline STA work.
  • Acacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost.

Matching Summary

Match Score: 75

** Cisco is seeking an ASIC Design Engineer for its Acacia team, focusing on high-speed optical interconnect products. The role involves developing extraction and static timing analysis methodologies while collaborating with the Physical Design team. **

Salary

Base: $135,800.00 - $252,000.00; Bonus/Equity: Not specified; Benefits: Medical, dental, vision, 401(k) with match, paid parental leave, etc.

Skills & Requirements

Must-have

  • Static Timing Analysis (STA)
  • Verilog/SystemVerilog programming
  • ASIC Design experience

Nice-to-have

  • Strong written and verbal communication skills
  • Correlation between PNR, Spice, and STA

Key Requirements

  • Bachelor's degree in Electrical or Computer engineering and 5+ years of ASIC Design experience
  • Master's degree in Electrical or Computer Engineering and 3+ years of experience
  • PhD + 0 years of experience
  • Experience with Verilog/SystemVerilog programming

Work Rights

Not specified

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