Senior Hardware Verification Engineer

NXP USA INC.

Uvm-based testbench architecture
Systemverilog verification environment
Functional coverage closure process
The role involves architecting advanced UVM-based testbenches for the end-to-end functional verification of complex digital SoC designs

Job Summary

  • The role involves architecting advanced UVM-based testbenches for the end-to-end functional verification of complex digital SoC designs.
  • Candidates will lead the coverage closure process to ensure all architectural specifications are met before tape-out.
  • The position requires integrating formal verification tools like JasperGold and hardware emulation platforms such as Palladium for system testing.

Matching Summary

The role involves architecting advanced UVM-based testbenches for the end-to-end functional verification of complex digital SoC designs.

Skills & Requirements

Must-have

  • UVM-based testbench architecture
  • SystemVerilog verification environment
  • Functional coverage closure process
  • Constrained-random stimulus development
  • JasperGold or VC Formal integration
  • Hardware emulation with Palladium

Nice-to-have

  • Mentorship of junior engineers
  • Code review leadership
  • Power-aware UPF/CPF verification
  • Collaboration with RTL designers
  • Throughput and latency analysis

Key Requirements

  • Experience with SystemVerilog and UVM
  • Background in ASIC hardware verification
  • Knowledge of formal verification methodologies

Work Rights

Not specified

Tailored Resume

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