Asic Design Engineer

Celerocommunicationsinc

Ottawa, Argentina
On-site
Hdl verilog system verilog proficiency
Digital circuit design implementation
Synthesis timing analysis lint formal equivalence
Celero Communications Inc. is seeking an experienced ASIC Design Engineer to contribute to the development of optical transceivers for next-generation optical modems. The ideal candidate should have at least four years of experience in digital design and verification, with proficiency in HDL languages and a strong understanding of digital design principles

Job Summary

  • The role involves designing and developing ASICs for next-generation optical modems and transceivers.
  • Candidates will perform synthesis, timing analysis, and Clock Domain Crossing (CDC) analysis to optimize designs.
  • The ideal candidate must have a Bachelor's degree and over four years of experience in digital design.

Matching Summary

Match Score: 85

Celero Communications Inc. is seeking an experienced ASIC Design Engineer to contribute to the development of optical transceivers for next-generation optical modems. The ideal candidate should have at least four years of experience in digital design and verification, with proficiency in HDL languages and a strong understanding of digital design principles.

Skills & Requirements

Must-have

  • HDL Verilog System Verilog proficiency
  • Digital circuit design implementation
  • Synthesis timing analysis Lint formal equivalence
  • Clock Domain Crossing CDC analysis
  • RTL simulation and verification experience
  • PPA optimization techniques

Nice-to-have

  • Low-power design techniques knowledge
  • UVM formal verification familiarity
  • DSP Digital Communication FEC knowledge
  • Python Tcl scripting languages
  • Optical Communication Standards understanding
  • Fast-paced dynamic environment adaptability

Key Requirements

  • Bachelor's or higher degree in Electrical Engineering
  • 4+ years of experience in digital design and verification
  • Proficiency in HDLs such as Verilog or System Verilog

Work Rights

Not specified

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