Own the verification lifecycle for one or more IPs/subsystems/SoC top-level features, including requirements decomposition, test plan definition, coverage strategy, execution, and signoff
Job Summary
Own the verification lifecycle for one or more IPs/subsystems/SoC top-level features, including requirements decomposition, test plan definition, coverage strategy, execution, and signoff.
Architect and implement UVM environments with scalable, reusable components, and develop test content including constrained-random sequences, scenario tests, and checkers.
Collaborate cross-functionally with RTL design, architecture, DV, DFT, performance, firmware, and post-silicon validation to ensure feature completeness and testability.
Matching Summary
Own the verification lifecycle for one or more IPs/subsystems/SoC top-level features, including requirements decomposition, test plan definition, coverage strategy, execution, and signoff.
Skills & Requirements
Must-have
UVM testbench development
constrained-random test content
coverage closure
debug across levels
SystemVerilog expertise
Python scripting proficiency
Nice-to-have
SoC-level verification experience
assertion-based verification
power-aware verification
emulation/FPGA prototyping
leading small teams
Key Requirements
5+ years of SoC/IP design verification experience
BS/MS in Electrical/Computer Engineering or related field