Soc/ip Design Verification Engineer

Intel

Guadalajara, Mexico
Hybrid
Uvm/systemverilog testbench development
Coverage-driven verification expertise
Debug skills in simulation/emulation
Own the verification lifecycle for one or more IPs/subsystems/SoC top-level features, including requirements decomposition, test plan definition, coverage strategy, execution, and signoff

Job Summary

  • Own the verification lifecycle for one or more IPs/subsystems/SoC top-level features, including requirements decomposition, test plan definition, coverage strategy, execution, and signoff.
  • Collaborate cross-functionally with RTL design, architecture, DV, DFT, performance, firmware, and post-silicon validation to ensure feature completeness and testability.
  • Continuously improve flows by contributing to methodology, regressions, CI/CD, and verification infrastructure.

Matching Summary

Own the verification lifecycle for one or more IPs/subsystems/SoC top-level features, including requirements decomposition, test plan definition, coverage strategy, execution, and signoff.

Skills & Requirements

Must-have

  • UVM/SystemVerilog testbench development
  • Coverage-driven verification expertise
  • Debug skills in simulation/emulation
  • Test planning and execution
  • Scripting for automation

Nice-to-have

  • Problem-solving mindset
  • Collaboration skills
  • Adaptability and learning agility
  • Attention to detail
  • Results-oriented approach

Key Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering or related field
  • 5+ years of SoC/IP design verification experience
  • Unrestricted, permanent right to work in Mexico

Work Rights

Must have unrestricted, permanent right to work in Mexico

Tailored Resume

Cover Letter