(md10)mcu數位ic驗證工程師

Nuvoton

Zhubei, TW
On-site
System verilog
Uvm
Ovl
Build Verification environment with DV language (eg. System Verilog, UVM etc)

Job Summary

  • Build Verification environment with DV language (eg. System Verilog, UVM etc).
  • Improve code or functional coverage and behavioral modeling of a digital or analog IP.
  • Lead a test case and build the test plan, improve or build up DV automation flow.

Matching Summary

Build Verification environment with DV language (eg. System Verilog, UVM etc).

Skills & Requirements

Must-have

  • System Verilog
  • UVM
  • OVL
  • SVA
  • NCSIM
  • NCVerilog
  • IRUN
  • VCS
  • Verdi

Nice-to-have

  • Behavioral modeling
  • Formal verification
  • DV automation flow
  • Palladium

Key Requirements

  • Master's degree
  • 3-5 years of experience
  • 5-10 years of experience

Work Rights

Not specified

Tailored Resume

Cover Letter