Lead Digital Verification Engineer

Cadence

Edinburgh, Scotland, United Kingdom
Competitive salary; not specified; 25 days holiday...
System verilog proficiency
Constrained-random verification techniques
Metric driven verification experience
The role focuses on defining and supporting the adoption of cutting-edge verification tools with a specific emphasis on AI and Machine Learning

Job Summary

  • The role focuses on defining and supporting the adoption of cutting-edge verification tools with a specific emphasis on AI and Machine Learning.
  • Candidates will develop generative AI tools to create and update UVM and Formal verification environments while optimizing regression processes.
  • Cadence offers competitive compensation including 25 days holiday, private medical plans, and an Employee Stock Purchase Plan.

Matching Summary

The role focuses on defining and supporting the adoption of cutting-edge verification tools with a specific emphasis on AI and Machine Learning.

Salary

Competitive salary; Not specified; 25 days holiday per year; Private Medical and Dental plans; Group Personal Pension Plan

Skills & Requirements

Must-have

  • System Verilog proficiency
  • Constrained-random verification techniques
  • Metric Driven Verification experience
  • UVM environment development
  • 4+ years microelectronics industry experience

Nice-to-have

  • Formal verification experience
  • Python scripting proficiency
  • AI agent development knowledge
  • ISO 26262 functional safety familiarity
  • Change management methodology skills

Key Requirements

  • Degree in Electrical/Electronic Engineering or related discipline
  • Minimum 4 years of experience in microelectronics/EDA industry
  • Strong spoken and written English communication skills

Work Rights

Not specified

Tailored Resume

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