Soc Physical Design Timing Engineer

Intel

Bangalore, India
Hybrid
Sta and timing closure activities
Primetime tool experience
Tcl perl shell scripting skills
The candidate will be responsible for Static Timing Analysis (STA) and timing closure activities for Intel SoCs and partitions

Job Summary

  • The candidate will be responsible for Static Timing Analysis (STA) and timing closure activities for Intel SoCs and partitions.
  • This role requires hands-on experience with industry standard tools like Primetime and strong scripting skills in TCL, Perl, or Shell.
  • Candidates must possess a Bachelor's or Master's degree in Electrical/Electronics Engineering with over 10 years of relevant experience.

Matching Summary

The candidate will be responsible for Static Timing Analysis (STA) and timing closure activities for Intel SoCs and partitions.

Skills & Requirements

Must-have

  • STA and timing closure activities
  • Primetime tool experience
  • TCL Perl Shell scripting skills
  • SoC cycle understanding
  • Synchronous asynchronous path analysis

Nice-to-have

  • Strong analytical problem solving skills
  • Self-motivated with initiative
  • Driving new methodologies
  • Ability to multitask effectively
  • Team working in diverse environment

Key Requirements

  • Bachelor or Master of Engineering degree
  • 10+ years of Physical Implementation experience
  • Timing Closure expertise required
  • Electrical or Electronics Engineering background

Work Rights

Not specified

Tailored Resume

Cover Letter