Layout Design Intern (summer 2026)

Ciena Corporation

Hourly: $25.00 – $34.00; bonus/equity: not specifi...
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Custom analog and mixed-signal layout design
Deep sub-micron cmos technologies
Cadence virtuoso and siemens calibre tools
** Ciena Corporation is seeking a Layout Design Intern for the summer of 2026, offering an opportunity to work on high-speed circuit design within a collaborative environment. The intern will gain hands-on experience in analog and mixed-signal layout design, contributing to next-generation products while being part of a company that prioritizes individual growth and social impact. **

Job Summary

  • This role offers hands-on exposure to advanced high-speed analog and mixed-signal circuit design within a team that has pioneered world-first DAC and ADC analog macros.
  • The intern will contribute directly to next-generation high-speed circuit development by executing comprehensive physical verification including DRC, LVS, electromigration, and IR drop analysis.
  • Ciena provides a flexible work environment focused on individual growth, well-being, and belonging, along with competitive compensation and paid benefits.

Matching Summary

Match Score: 75

** Ciena Corporation is seeking a Layout Design Intern for the summer of 2026, offering an opportunity to work on high-speed circuit design within a collaborative environment. The intern will gain hands-on experience in analog and mixed-signal layout design, contributing to next-generation products while being part of a company that prioritizes individual growth and social impact. **

Salary

Hourly: $25.00 – $34.00; Bonus/Equity: Not specified; Benefits: EAP access, company-paid holidays, paid sick leave, vacation pay

Skills & Requirements

Must-have

  • Custom analog and mixed-signal layout design
  • Deep sub-micron CMOS technologies
  • Cadence Virtuoso and Siemens Calibre tools
  • DRC, LVS, EM, and IR drop analysis
  • Floorplanning and device matching techniques

Nice-to-have

  • High-speed data converter or PLL layout experience
  • BiCMOS technology familiarity
  • PERL or SKILL scripting for automation
  • Cross-functional hardware team collaboration
  • Proactive identification of layout-sensitive structures

Key Requirements

  • Currently pursuing degree in Electrical Engineering or related field
  • Experience with deep sub-micron CMOS technologies
  • Proficiency interpreting DRC and LVS reports

Work Rights

Not specified

Tailored Resume

Cover Letter