Senior Sta Timing Engineer

Cisco UK

Static timing analysis sta experience
Sdc constraint development in test modes
Primetime tool proficiency
The team is dedicated to ensuring robust and accurate timing constraints for advanced chip designs within a collaborative environment

Job Summary

  • The team is dedicated to ensuring robust and accurate timing constraints for advanced chip designs within a collaborative environment.
  • You will own the creation and validation of timing constraints at block, sub-chip, and full-chip levels across various test modes.
  • Cisco offers limitless opportunities to grow and build solutions that power how humans and technology work together globally.

Matching Summary

The team is dedicated to ensuring robust and accurate timing constraints for advanced chip designs within a collaborative environment.

Skills & Requirements

Must-have

  • Static Timing Analysis STA experience
  • SDC constraint development in test modes
  • PrimeTime tool proficiency
  • Scripting in Perl TCL Python
  • Block full-chip timing validation

Nice-to-have

  • Debugging DFT mode timing constraints
  • Synopsys Fusion Compiler experience
  • Tessent DFT insertion knowledge
  • Cross-functional collaboration skills
  • Innovation and continuous learning mindset

Key Requirements

  • Bachelor's degree with 8+ years experience or Master's with 6+ years
  • Proficiency in at least two scripting languages like Perl or Python
  • Proven track record in SDC validation and timing exception handling

Work Rights

Not specified

Tailored Resume

Cover Letter