Lead Dft Engineer

NXP USA INC.

Dft methodologies: scan, mbist, lbist, jtag
Atpg tools
Low-power dft
You will be responsible for designing, implementing, and verifying DFT architectures for complex SoCs

Job Summary

  • You will be responsible for designing, implementing, and verifying DFT architectures for complex SoCs.
  • You will work closely with RTL, physical design, and verification teams to ensure robust testability and high-quality silicon.
  • Work with ATE teams for test program development and silicon bring-up.

Matching Summary

You will be responsible for designing, implementing, and verifying DFT architectures for complex SoCs.

Skills & Requirements

Must-have

  • DFT methodologies: Scan, MBIST, LBIST, JTAG
  • ATPG tools
  • low-power DFT
  • fault models
  • physical design constraints

Nice-to-have

  • SoC level DFT experience
  • high-speed interfaces
  • mixed-signal blocks

Key Requirements

  • Bachelor’s or Master’s in Electrical/Electronics Engineering
  • Silicon debug and ATE bring-up experience

Work Rights

Not specified

Tailored Resume

Cover Letter