Dfx Design Architect

Altera

Penang, Malaysia
Dfx architect
Fpga and soc families
Ieee 1687 (ijtag)
Define and document DFX architectures for multi-die (chiplet) systems, high-speed transceivers, and massive FPGA fabrics

Job Summary

  • Define and document DFX architectures for multi-die (chiplet) systems, high-speed transceivers, and massive FPGA fabrics.
  • Lead the definition of on-chip debug infrastructures to enable rapid root-cause analysis of complex silicon failures.
  • Influence EDA vendors to align their roadmaps with Altera’s specific FPGA architectural needs.

Matching Summary

Define and document DFX architectures for multi-die (chiplet) systems, high-speed transceivers, and massive FPGA fabrics.

Skills & Requirements

Must-have

  • DFX Architect
  • FPGA and SoC families
  • IEEE 1687 (IJTAG)
  • High-Speed Link Testing (HSLT)
  • Test Cost Optimization
  • Silicon Debug

Nice-to-have

  • Technical beacon
  • Strategic thinking
  • Stakeholder management
  • Problem solving

Key Requirements

  • 10–12 years of hands-on experience in DFT/DFD
  • 4 years in an architectural or lead capacity
  • BS/MS or Ph.D. in Electrical/Electronics/Computer Engineering
  • ASIL-D functional safety standards
  • Tcl/Python scripting proficiency

Work Rights

Not specified

Tailored Resume

Cover Letter