Engineer / Senior Engineer, Physical Design (asic Place & Route) (san Jose, Ca) (7429)

TSMC

San Jose, California, USA
Base: $110,000 - $160,000 py; bonus/equity: not sp...
On-site
Rtl-to-gds physical implementation
Synthesis, floorplan, place and route
Clock tree synthesis (cts)
As a Physical Design Engineer, you will be responsible for the entire APR implementation flow from RTL-to-GDS that includes synthesis, floorplan, place and route, CTS, STA, and signoff

Job Summary

  • As a Physical Design Engineer, you will be responsible for the entire APR implementation flow from RTL-to-GDS that includes synthesis, floorplan, place and route, CTS, STA, and signoff.
  • We are currently operating in a hybrid work schedule with 4 days in office.
  • TSMC’s total compensation package consists of market competitive pay, allowances, bonuses, and comprehensive benefits.

Matching Summary

As a Physical Design Engineer, you will be responsible for the entire APR implementation flow from RTL-to-GDS that includes synthesis, floorplan, place and route, CTS, STA, and signoff.

Salary

Base: $110,000 - $160,000 per year; Bonus/Equity: Not specified; Benefits: Comprehensive benefits

Skills & Requirements

Must-have

  • RTL-to-GDS physical implementation
  • Synthesis, floorplan, place and route
  • Clock tree synthesis (CTS)
  • Static timing analysis (STA)
  • Signal EM/Noise analysis
  • Power IR/EM analysis
  • DRC/LVS/ERC/ANTENNA analysis

Nice-to-have

  • Low-power implementation methodology
  • Advanced timing signoff methodology
  • 3D IC technologies

Key Requirements

  • 3+ years of industry experience
  • Master’s degree in Electrical/Computer Science Engineering
  • Experience with TSMC N16 or below technology
  • Experience in block level implementation or chip integration and signoff
  • Experience in Perl/TCL language programming

Work Rights

Not specified

Tailored Resume

Cover Letter