Job Summary

• Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks.
• Mentor and coach early-in-career engineers in front-end ASIC development, driving continuous improvement in technical skills and execution.
• At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.

Matching Summary

Salary

Base: $149,100.00 - $218,900.00; Bonus/Equity: Not specified; Benefits: Medical, dental, vision, 401(k) with match, paid parental leave, disability, life insurance, stock options, paid time off

Skills & Requirements

Key Requirements

• 8+ years ASIC experience (Bachelor's)
• 6+ years ASIC experience (Master's)
• Block/subsystem RTL development experience
• Static Timing Analysis experience
• Experience with STA tools like PrimeTime/Tempus
• Experience with synthesis tools
• Verilog/System Verilog programming

Work Rights