The team is focused on producing world-class Wireless MCU products including custom RISC-V Cores and AI/ML accelerators
Job Summary
The team is focused on producing world-class Wireless MCU products including custom RISC-V Cores and AI/ML accelerators.
Candidates must create and execute verification plans using constrained random tests, scoreboards, and coverage analysis to validate block power and performance.
The role offers a highly competitive salary range of $150,500 to $279,500 along with equity rewards and comprehensive benefits.
Matching Summary
The team is focused on producing world-class Wireless MCU products including custom RISC-V Cores and AI/ML accelerators.
Salary
Base: $150,500 - $279,500 USD; Bonus/Equity: Annual cash bonus and RSUs included; Benefits: Medical dental vision 401k match flexible PTO
Skills & Requirements
Must-have
10+ years design experience
UVM test bench development from scratch
Verilog SystemVerilog C/C++ knowledge
Constrained random stimulus and coverage analysis
Formal verification tools lint auto property checks
Nice-to-have
AI powered tools experience
Mixed signal verification with RNM SPICE
Low power design debug with UPF
Technical leadership and mentoring skills
RISC-V architecture knowledge
Key Requirements
Bachelor's or Master's degree in Electrical/Computer Engineering