High-speed I/o Phy Architect

Intel

Folsom, California, US
Base: $220,920.00-361,480.00 usd; bonus/equity: st...
High-speed i/o phy architecture
Pcie, cxl, usbx, display, mipi, ethernet, tsn
Ip evaluation and selection
Lead the architectural definition and integration of high-speed PHYs for client SoCs, including PCIe, CXL, USBx, Display, MIPI, Ethernet, and TSN

Job Summary

  • Lead the architectural definition and integration of high-speed PHYs for client SoCs, including PCIe, CXL, USBx, Display, MIPI, Ethernet, and TSN.
  • Conduct technical evaluations of both internal and external PHY IPs, analyzing their performance characteristics against product requirements.
  • Serve as a technical lead in the post-silicon debug and validation of high-speed I/O interfaces, leading taskforces and driving the resolution of complex issues.

Matching Summary

Lead the architectural definition and integration of high-speed PHYs for client SoCs, including PCIe, CXL, USBx, Display, MIPI, Ethernet, and TSN.

Salary

Base: $220,920.00-361,480.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Must-have

  • High-Speed I/O PHY Architecture
  • PCIe, CXL, USBx, Display, MIPI, Ethernet, TSN
  • IP Evaluation and Selection
  • Technical Documentation and Specifications
  • Post-Silicon Debug and Validation

Nice-to-have

  • Strategic Acumen
  • Cross-functional Collaboration
  • Influence Senior Stakeholders
  • Technology Vision and Research

Key Requirements

  • BS degree in Electrical/Computer Engineering with 15 years of experience
  • Master's or PhD degree in Electrical/Computer Engineering with 12 years of experience
  • Prior hands-on experience in High-Speed IO PHY Architecture and Design
  • Strong knowledge in interoperability of HSIO PHYs

Work Rights

Not specified

Tailored Resume

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