Current salary including aws or variable bonus req...
Not specified (assume hybrid or onsite based on location and nature of work).
Vhdl/verilog digital logic design
Rtl design for soc and fpga
Low power upf/cpf input standards
MAXLINEAR ASIA SINGAPORE PRIVATE LIMITED is seeking a SOC Design Engineer, welcoming fresh graduates to apply. The role involves designing digital logic using VHDL/Verilog and requires a solid understanding of SoC design, verification, and low-power requirements
Job Summary
The role involves designing high-quality RTL that meets strict I/O requirements, constraints, and multiple clock domains for complex SoCs.
Candidates must have experience in the complete DSM SoC design cycle from conception through silicon validation across various process nodes.
Fresh graduates are welcome to apply, though extensive experience with several million-gate count SoCs is essential for this position.
Matching Summary
Match Score: 75
MAXLINEAR ASIA SINGAPORE PRIVATE LIMITED is seeking a SOC Design Engineer, welcoming fresh graduates to apply. The role involves designing digital logic using VHDL/Verilog and requires a solid understanding of SoC design, verification, and low-power requirements.
Salary
Current salary including AWS or Variable Bonus required; Expected salary required
Skills & Requirements
Must-have
VHDL/Verilog digital logic design
RTL design for SoC and FPGA
Low power UPF/CPF input standards
DSM process node experience (65-16nm)
Complete SoC design cycle and tape-out
Nice-to-have
Experience with GPS, WLAN, BT, NFC
SoC Clock & Reset structure design
Design For Test (DFT) requirements
Synthesis and Logic Equivalent checks
Core Consultant connectivity tools
Key Requirements
Bachelor or Master's in Electrical/Electronics Engineering
Experience with 65, 45, 40, 28, 16nm process nodes
Several million-gates-count complex SoC tape-out experience