Job Summary

• Shape the future of programmable logic by delivering high-performance, power-efficient FPGA solutions.
• Architect and optimize advanced ASIC/FPGA implementation flows, focusing on timing and power convergence, leveraging ML/AI.
• This is a highly visible, cross-functional position working closely with design, physical design, CAD, library, and reliability teams.

Matching Summary

Salary

$127,400 - $184,400 USD; Not specified; Not specified

Skills & Requirements

Key Requirements

• 8+ years of experience in ASIC or FPGA timing/power/library flow development
• 6+ years of experience in timing and power flow development
• 6+ years of experience with STA, power analysis, and library characterization tools
• 6+ years of experience with Tcl, Python, Perl, or similar coding
• 6+ years of experience with timing concepts and constraints
• 6+ years of experience in power analysis and optimization
• 6+ years of hands-on experience with library generation and characterization
• 6+ years of experience working with UPF
• Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
• Eligible for U.S. export authorizations

Work Rights