Master's Thesis Student – Digital Control-loop Development For Space Applications (d/f/m)

Airbus Defence and Space GmbH

Friedrichshafen, Germany
Fpga-based digital control systems
Vhdl and c code within xilinx fpga/vivado
Adaptive control strategies
Implement VHDL and C code within the Xilinx FPGA/VIVADO environment, further develop and optimize the existing FPGA-based control system, including the implementation of adaptive control strategies for different operational conditions and the design of suitable interface electronics (analogue and digital)

Job Summary

  • Implement VHDL and C code within the Xilinx FPGA/VIVADO environment, further develop and optimize the existing FPGA-based control system, including the implementation of adaptive control strategies for different operational conditions and the design of suitable interface electronics (analogue and digital).
  • Set up a graphical user interface (GUI) to visualize and monitor the system’s real-time performance and document development steps and results in a structured and reproducible manner.
  • Attractive salary and work-life balance with an 35-hour week (flexitime), international environment with the opportunity to network globally, and work with modern/diversified technologies.

Matching Summary

Implement VHDL and C code within the Xilinx FPGA/VIVADO environment, further develop and optimize the existing FPGA-based control system, including the implementation of adaptive control strategies for different operational conditions and the design of suitable interface electronics (analogue and digital).

Skills & Requirements

Must-have

  • FPGA-based digital control systems
  • VHDL and C code within Xilinx FPGA/VIVADO
  • adaptive control strategies
  • interface between FPGA and real-world applications
  • graphical user interface (GUI) for system monitoring
  • digital signal processing and/or control theory

Nice-to-have

  • international environment with global networking
  • work-life balance with 35-hour week
  • corporate sports groups
  • participation in Generation Airbus Community

Key Requirements

  • Master’s program enrollment
  • Electrical Engineering, Communications Engineering, Computer Science, Physics, or related field
  • Proven practical experience in FPGA development with VHDL/Verilog
  • Programming skills in C/C++, MATLAB, Python or similar
  • Good communication skills in English

Work Rights

Not specified

Tailored Resume

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