ISP RTL Design Engineer

OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD.

Singapore
Rtl design with verilog systemverilog
Isp algorithm implementation experience
Digital system level logic verification
The role involves implementing ISP algorithms into hardware using Verilog, SystemVerilog, and High Level Synthesis

Job Summary

  • The role involves implementing ISP algorithms into hardware using Verilog, SystemVerilog, and High Level Synthesis.
  • Candidates will verify logic at both the ISP and Digital System levels while optimizing for gate count and power consumption.
  • Success requires close collaboration with the ISP Algorithm Team to drive design activities effectively.

Matching Summary

Match Score: 85

The role involves implementing ISP algorithms into hardware using Verilog, SystemVerilog, and High Level Synthesis.

Skills & Requirements

Must-have

  • RTL Design with Verilog SystemVerilog
  • ISP Algorithm implementation experience
  • Digital System level logic verification
  • High Level Synthesis with SystemC

Nice-to-have

  • CMOS Image Sensor domain knowledge
  • Strong debugging and problem-solving skills
  • Adaptable to changes in project scope

Key Requirements

  • Minimum MSEE or BSEE degree required
  • Experience in C/C++ programming
  • Strong background in RTL verification

Work Rights

Not specified

Tailored Resume

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