As an ASIC layout designer, you will be responsible for analog layout design from block level, up to top level IC integration and physical verification for advanced ASIC in MEMS sensor
Job Summary
As an ASIC layout designer, you will be responsible for analog layout design from block level, up to top level IC integration and physical verification for advanced ASIC in MEMS sensor.
You will work with international design team to ensure the layout delivery on time and in quality, then execute whole tape-out flow together with wafer foundry.
You will also work with CAD engineers to continuously improve our PDKs and design environment.
Matching Summary
As an ASIC layout designer, you will be responsible for analog layout design from block level, up to top level IC integration and physical verification for advanced ASIC in MEMS sensor.
Skills & Requirements
Must-have
analog layout design
top level IC integration
physical verification
Cadence Virtuoso platform
Mentor Graphics verification tools
CMOS process side effect understanding
scripting for layout efficiency
Nice-to-have
improve quality of life
work with international design team
continuously improve PDKs
strong problem-solving skills
fluent English
Key Requirements
Bachelor or master degree
8 or above years’ experience
TSMC28nm ~ 152nm, SMIC110nm, TZ 180nm BCD SOI technologies
Proficiency with Cadence and Mentor Graphics verification and extraction tools