Design Engineer – Ai Soc Development

Intel

Folsom, California, United States
Base: $164,470.00-232,190.00 usd; bonus/equity: st...
Hybrid
Rtl design and implementation for asic/soc
Proficiency in verilog/system verilog coding
Experience with synthesis tools and timing closure
Join Intel's AI SoC organization to develop cutting-edge products powering AI applications from edge devices to data center accelerators

Job Summary

  • Join Intel's AI SoC organization to develop cutting-edge products powering AI applications from edge devices to data center accelerators.
  • You will implement RTL in Verilog/System Verilog based on defined micro-architecture and integrate IP blocks at the top level.
  • The role offers a competitive total compensation package including stock bonuses, health benefits, and a hybrid work model.

Matching Summary

Join Intel's AI SoC organization to develop cutting-edge products powering AI applications from edge devices to data center accelerators.

Salary

Base: $164,470.00-232,190.00 USD; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, and vacation programs

Skills & Requirements

Must-have

  • RTL design and implementation for ASIC/SoC
  • Proficiency in Verilog/System Verilog coding
  • Experience with synthesis tools and timing closure

Nice-to-have

  • Understanding of clock domain crossings
  • Familiarity with standard bus protocols like AXI
  • Hands-on experience with formal verification tools
  • Basic scripting skills in Python or TCL
  • Strong problem-solving and collaborative mindset

Key Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science
  • 4+ years of experience in RTL design and implementation for ASIC/SoC development

Work Rights

Not specified

Tailored Resume

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